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MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
MC14060B 14-Bit Binary Counter and Oscillator
The MC14060B is a 14-stage binary ripple counter with an on-chip oscillator buffer. The oscillator configuration allows design of either RC or crystal oscillator circuits. Also included on the chip is a reset function which places all outputs into the zero state and disables the oscillator. A negative transition on Clock will advance the counter to the next state. Schmitt trigger action on the input line permits very slow input rise and fall times. Applications include time delay circuits, counter controls, and frequency dividing circuits. * * * * Fully static operation Diode Protection on All Inputs Supply Voltage Range = 3.0 V to 18 V Capable of Driving Two Low-power TTL Loads or One Low-power Schottky TTL Load Over the Rated Temperature Range * Buffered Outputs Available from Stages 4 Through 10 and 12 Through 14 * Common Reset Line * Pin-for-Pin Replacement for CD4060B TRUTH TABLE
Clock Reset L L H Output State No Change Advance to next state All Outputs are low Q12 Q13 Q14 Q6 Q5 Q7 Q4 VSS 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 VDD Q10 Q8 Q9 RESET CLOCK OUT 1 OUT 2 L SUFFIX CERAMIC CASE 620
P SUFFIX PLASTIC CASE 648
D SUFFIX SOIC CASE 751B
ORDERING INFORMATION
MC14XXXBCP MC14XXXBCL MC14XXXBD Plastic Ceramic SOIC
TA = - 55 to 125C for all packages.
PIN ASSIGNMENT
X
X = Don't Care
LOGIC DIAGRAM
OUT 2 9 OUT 1 10 CLOCK 11 C C RESET 12 Q6 = PIN 4 Q7 = PIN 6 Q8 = PIN 14 Q9 = PIN 13 Q10 = PIN 15 VDD = PIN 16 VSS = PIN 8 Q Q C C Q Q C C Q Q C C Q Q C C Q Q C C Q Q Q4 7 Q5 5 Q12 1 Q13 2 Q14 3
R
R
R
R
R
R
REV 3 1/94
(c)MOTOROLA CMOS LOGIC DATA Motorola, Inc. 1995
MC14060B 1
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# Data labelled "Typ" is not to be used for design purposes but is intended as an indication of the IC's potential performance. ** The formulas given are for the typical characteristics only at 25_C. * Maximum Ratings are those values beyond which damage to the device may occur. Temperature Derating: Plastic "P and D/DW" Packages: - 7.0 mW/_C From 65_C To 125_C Ceramic "L" Packages - 12 mW/_C From 100_C To 125_C
ELECTRICAL CHARACTERISTICS (Voltages Referenced to VSS)
MAXIMUM RATINGS* (Voltages Referenced to VSS)
Total Supply Current** (Dynamic plus Quiescent, Per Package) (CL = 50 pF on all outputs, all buffers switching)
Quiescent Current (Per Package)
Input Capacitance (Vin = 0)
Input Current
Output Drive Current (VOH = 2.5 V) (Except Source (VOH = 4.6 V) Pins 9 and 10) (VOH = 9.5 V) (VOH = 13.5 V)
Input Voltage "0" Level (VO = 4.5 Vdc) (For Input 11 (VO = 9.0 Vdc) and Output 10) (VO = 13.5 Vdc)
Input Voltage (VO = 4.5 or 0.5 V) (VO = 9.0 or 1.0 V) (VO = 13.5 or 1.5 V)
Output Voltage Vin = VDD or 0
Vin, Vout
MC14060B 2
Symbol Iin, Iout VDD Tstg PD (VO = 0.5 Vdc) (VO = 1.0 Vdc) (VO = 1.5 Vdc) (VO = 0.5 or 4.5 V) (VO = 1.0 or 9.0 V) (VO = 1.5 or 13.5 V) (VOL = 0.4 V) (VOL = 0.5 V) (VOL = 1.5 V) Vin = 0 or VDD TL Characteristic Lead Temperature (8-Second Soldering) Storage Temperature Power Dissipation, per Package Input or Output Current (DC or Transient), per Pin Input or Output Voltage (DC or Transient) DC Supply Voltage "1" Level "1" Level "1" Level "0" Level "0" Level Parameter Sink Symbol VOH VOL IOH IDD VIH VIH IOL Cin VIL VIL Iin IT VDD Vdc 5.0 10 15 5.0 10 15 5.0 10 15 5.0 5.0 10 15 5.0 10 15 5.0 10 15 5.0 10 15 5.0 10 15 5.0 10 15 5.0 10 15 15 -- - 0.5 to VDD + 0.5 - 3.0 - 0.64 - 1.6 - 4.2 - 0.5 to + 18.0 4.95 9.95 14.95 - 65 to + 150 4.0 8.0 12.5 0.64 1.6 4.2 3.5 7.0 11.0 - 55_C Min Max -- -- -- -- -- -- -- -- -- -- -- -- -- -- Value 10 260 500 0.1 0.05 0.05 0.05 5.0 10 20 1.0 2.0 2.5 1.5 3.0 4.0 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Unit mW mA - 2.4 - 0.51 - 1.3 - 3.4
_C
_C
4.95 9.95 14.95
V
V
4.0 8.0 12.5
0.51 1.3 3.4
3.5 7.0 11.0
IT = (0.25 A/kHz) f + IDD IT = (0.54 A/kHz) f + IDD IT = (0.85 A/kHz) f + IDD
Min
-- -- --
--
--
-- -- --
-- -- --
-- -- --
0.00001
- 4.2 - 0.88 - 2.25 - 8.8
This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high-impedance circuit. For proper operation, Vin and Vout should be constrained to the range VSS (Vin or Vout) VDD. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either VSS or VDD). Unused outputs must be left open.
25_C Typ #
0.005 0.010 0.015
0.88 2.25 8.8
2.75 5.50 8.25
2.25 4.50 6.75
2.75 5.50 8.25
2.25 4.50 6.75
5.0
5.0 10 15
0 0 0
MOTOROLA CMOS LOGIC DATA
0.1 0.05 0.05 0.05 Max 5.0 10 20 7.5 1.0 2.0 2.5 1.5 3.0 4.0 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
v
- 1.7 - 0.36 - 0.9 - 2.4
4.95 9.95 14.95
4.0 8.0 12.5
0.36 0.9 2.4
3.5 7.0 11.0
125_C Min Max
-- -- -- -- -- -- -- -- -- -- -- -- -- --
1.0
0.05 0.05 0.05
150 300 600 1.0 2.0 2.5 1.5 3.0 4.0 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
v
Unit
Vdc
Vdc
mA
mA
A A A V V V V pF
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#Data labelled "Typ" is not to be used for design purposes but is intended as an indication of the IC's potential performance.
SWITCHING CHARACTERISTICS (CL = 50 pF, TA = 25_C)
Propagation Delay Time Reset to On
Reset Pulse Width
Clock Rise and Fall Time
Clock Pulse Frequency
Clock Pulse Width
Propagation Delay Time Clock to Q4
Output Fall Time (Counter Outputs)
Output Rise Time (Counter Outputs)
MOTOROLA CMOS LOGIC DATA
Clock to Q14 CLOCK PULSE GENERATOR
Figure 1. Power Dissipation Test Circuit and Waveform
500 F
CLOCK
Characteristic
50% DUTY CYCLE
90% 50% 10%
NC NC
20 ns
Q4 OUT1 Q5 OUT2 Qn R
ID
VDD
VSS
0.01 F
20 ns
CL
CL
VSS
VDD
CL
Symbol
tPHL
tPLH tPHL
tTLH tTHL
tTHL
tTLH
twH
tw
f
PULSE GENERATOR
VDD Vdc
5.0 10 15
5.0 10 15
5.0 10 15
5.0 10 15
5.0 10 15
5.0 10 15
5.0 10 15
5.0 10 15
5.0 10 15
Figure 2. Switching Time Test Circuit and Waveforms
CLOCK
tTLH
Q
Min
120 60 40
100 40 30
CLOCK
-- -- --
-- -- --
-- -- --
-- -- --
-- -- --
-- -- --
20 ns
NC NC
90% 50% 10%
tPLH
Q4 OUT1 Q5 OUT2 Qn R
No Limit
Typ #
90% 50% 10%
170 80 60
415 175 125
VDD
1.5 0.7 0.4
5 14 17
40 15 10
65 30 20
50 30 20
40 25 20
VSS
tWH
tTHL
CL
Max
350 160 100
740 300 200
200 100 80
200 100 80
3.5 8 12
2.7 1.3 1.0
-- --
--
-- -- --
tPHL
MC14060B 3
20 ns CL MHz Unit s ns ns ns ns ns ns ns CL
CLOCK 11 f RESET 10 OUT 1 Rtc RS Ctc 9 OUT 2
[ 2.3 R1tcCtc
if 1 kHz f 100 kHz and 2Rtc < RS < 10Rtc (f in Hz, R in ohms, C in farads) The formula may vary for other frequencies. Recommended maximum value for the resistors in 1 M.
Figure 3. Oscillator Circuit Using RC Configuration
TYPICAL RC OSCILLATOR CHARACTERISTICS
8.0 FREQUENCY DEVIATION (%) 4.0 0 - 4.0 - 8.0 - 12 - 16 - 55
RTC = 56 k C = 1000 pF RS = 0, f = 10.15 kHz @ VDD = 10, TA = 25C RS = 120 k, f = 7.8 kHz @ VDD = 10 V, TA = 25C
100 f, OSCILLATOR FREQUENCY (kHz) VDD = 15 V 50 20 10 5 2 1 0.5 0.2 125 0.1 1.0 k 0.0001 10 k 100 k RTC, RESISTANCE (OHMS) 0.001 0.01 C, CAPACITANCE (F) 1.0 M 0.1 f AS A FUNCTION OF C (RTC = 56 k) (RS = 120 k) VDD = 10 V f AS A FUNCTION OF RTC (C = 1000 pF) (RS 2RTC)
1.0 V
5.0 V
- 25
0 25 50 75 TA, AMBIENT TEMPERATURE (C)
100
Figure 4. RC Oscillator Stability
CLOCK 11
RESET 18M RO CS CT
10 OUT 1
9 OUT 2
Figure 6. Typical Crystal Oscillator Circuit
MC14060B 4
IIIIIIIIIIIIIIII II I IIIIIIIIIIIIIIII II I IIIIIIIIIIIIIIII II I IIIIIIIIIIIIIIII II I IIIIIIIIIIIIIIII II I IIIIIIIIIIIIIIII II I IIIIIIIIIIIIIIII II I IIIIIIIIIIIIIIII II I III I I I IIIIIIIIIIIIIIII II I IIIIIIIIIIIIIIII II I IIIIIIIIIIIIIIII II I IIIIIIIIIIIIIIII IIIIIIIIIIIIII II IIIIIIIIIIIIIIII II I III I I I IIIIIIIIIIIIIIII II I IIIIIIIIIIIIIIII II I IIIIIIIIIIIIIIII II I IIIIIIIIIIIIIIII II I IIIIIIIIIIIIIIII II I IIIIIIIIIIIIIIII II I IIIIIIIIIIIIIIII IIIIIIIIIIIIII II IIIIIIIIIIIIIIII II I IIIIIIIIIIIIIIII II I IIIIIIIIIIIIIIII II I IIIIIIIIIIIIIIII II I IIIIIIIIIIIIIIII II I
Characteristic 500 kHz Circuit 32 kHz Circuit Unit Crystal Characteristics Resonant Frequency Equivalent Resistance, RS 500 1.0 32 6.2 kHz k External Resistor/Capacitor Values RO CT CS 47 82 20 750 82 20 k pF pF Frequency Stability Frequency Changes as a Function of VDD (TA = 25_C) VDD Change from 5.0 V to 10V VDD Change from 10 V to 15 V Frequency Change as a Function of Temperature (VDD = 10 V) TA Change from - 55_C to + 25_C Complete Oscillator* TA Change from + 25_C to + 125_C Complete Oscillator* + 6.0 + 2.0 + 2.0 + 2.0 ppm ppm + 100 - 160 + 120 - 560 ppm ppm * Complete oscillator includes crystal, capacitors, and resistors.
Figure 5. RC Oscillator Frequency as a Function of RTC and C
Figure 7. Typical Data for Crystal Oscillatgor Circuit
MOTOROLA CMOS LOGIC DATA
OUTLINE DIMENSIONS
L SUFFIX CERAMIC DIP PACKAGE CASE 620-10 ISSUE V
-A-
16 9 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION L TO CENTER OF LEAD WHEN FORMED PARALLEL. 4. DIMENSION F MAY NARROW TO 0.76 (0.030) WHERE THE LEAD ENTERS THE CERAMIC BODY. DIM A B C D E F G H K L M N INCHES MIN MAX 0.750 0.785 0.240 0.295 --- 0.200 0.015 0.020 0.050 BSC 0.055 0.065 0.100 BSC 0.008 0.015 0.125 0.170 0.300 BSC 0_ 15 _ 0.020 0.040 MILLIMETERS MIN MAX 19.05 19.93 6.10 7.49 --- 5.08 0.39 0.50 1.27 BSC 1.40 1.65 2.54 BSC 0.21 0.38 3.18 4.31 7.62 BSC 0_ 15 _ 0.51 1.01
-B-
1 8
C
L
-T-
SEATING PLANE
N E F D G
16 PL
K M J
16 PL
0.25 (0.010)
M
M
TB
S
0.25 (0.010)
TA
S
P SUFFIX PLASTIC DIP PACKAGE CASE 648-08 ISSUE R
-A-
16 9 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION L TO CENTER OF LEADS WHEN FORMED PARALLEL. 4. DIMENSION B DOES NOT INCLUDE MOLD FLASH. 5. ROUNDED CORNERS OPTIONAL. DIM A B C D F G H J K L M S INCHES MIN MAX 0.740 0.770 0.250 0.270 0.145 0.175 0.015 0.021 0.040 0.70 0.100 BSC 0.050 BSC 0.008 0.015 0.110 0.130 0.295 0.305 0_ 10 _ 0.020 0.040 MILLIMETERS MIN MAX 18.80 19.55 6.35 6.85 3.69 4.44 0.39 0.53 1.02 1.77 2.54 BSC 1.27 BSC 0.21 0.38 2.80 3.30 7.50 7.74 0_ 10 _ 0.51 1.01
B
1 8
F S
C
L
-T- H G D
16 PL
SEATING PLANE
K
J TA
M
M
0.25 (0.010)
M
MOTOROLA CMOS LOGIC DATA
MC14060B 5
OUTLINE DIMENSIONS
D SUFFIX PLASTIC SOIC PACKAGE CASE 751B-05 ISSUE J
-A-
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. MILLIMETERS MIN MAX 9.80 10.00 3.80 4.00 1.35 1.75 0.35 0.49 0.40 1.25 1.27 BSC 0.19 0.25 0.10 0.25 0_ 7_ 5.80 6.20 0.25 0.50 INCHES MIN MAX 0.386 0.393 0.150 0.157 0.054 0.068 0.014 0.019 0.016 0.049 0.050 BSC 0.008 0.009 0.004 0.009 0_ 7_ 0.229 0.244 0.010 0.019
16
9
-B-
1 8
P
8 PL
0.25 (0.010)
M
B
S
G F
K C -T-
SEATING PLANE
R
X 45 _
M D
16 PL M
J
0.25 (0.010)
TB
S
A
S
DIM A B C D F G J K M P R
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JAPAN: Nippon Motorola Ltd.; Tatsumi-SPD-JLDC, 6F Seibu-Butsuryu-Center, 3-14-2 Tatsumi Koto-Ku, Tokyo 135, Japan. 03-81-3521-8315 ASIA/PACIFIC: Motorola Semiconductors H.K. Ltd.; 8B Tai Ping Industrial Park, 51 Ting Kok Road, Tai Po, N.T., Hong Kong. 852-26629298
MC14060B 6
*MC14060B/D*
MOTOROLA CMOS LOGIC DATA MC14060B/D

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